An Automatic Built-In Self-Repair Compiler for Embedded Memories

• Main Authors: Shih-Chang Huang, 黃世昌
• Other Authors: Shyue-Kung Lu
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/80555629554266868074

碩士 === 輔仁大學 === 電子工程學系 === 93 === The reliabilities of embedded RAMs are becoming a major concern among the designers and fabrication since the yield of on-chip memories will dominate the chip yield. In general, fault-tolerant architectures are usually used to improve the yield for memory fabrication. Therefore, in this thesis, a novel built-in self-test and repair (BISTR) approach is first proposed for semiconductor memories with 1-D redundancy (redundant rows) structures. The memory rows (including the redundant rows) are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. Due to the nanometer technology, more subtle defects will exist in the embedded memories. In order to detect such defects, a new March test algorithm named March D which can detect all signal-cell static faults, signal-cell dynamic faults, and the traditional two-cell coupling faults is proposed. Moreover, in order to decrease the development time of the BISR circuit, an automatic BISR compiler based on virtual divided word line is also proposed. An experimental 256  512-bit SRAM chip with the proposed BISTR capability is designed and implemented with UMC 0.18 m 1P6M technology using Synopsys Design Compiler and Cadence Silicon Ensemble. According to the experimental result, the hardware overhead is 3.06%. If the capacity of the memories increases, the hardware overhead will decrease further.