Study of Low-Dielectric-Constant Materials on Process Integration of beyond sub-micro MOS Integrated Circuits
博士 === 國立交通大學 === 材料科學與工程系所 === 93 === Abstract As the device dimensions continue to shrink, interconnect delay becomes a limiting factor for increasing circuit device speed. Since interconnect delay is the product of the resistance in metal interconnect and the capacitance between the metal lines,...
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16757361068987272487 |