| Summary: | 碩士 === 國立交通大學 === 資訊科學系所 === 93 === Remarkable advances in the process and circuit designs bring crucial challenges for optimizing the layout of a multi-million gate design. Moreover, introducing System On a Chip (SOC) design methodology greatly increases the design complexity and the layout integration complexity of various Intelligent Properties (IPs). Delay and noise optimization are dominant factors to succeed in the design, where wire sizing and spacing are widely used for solving the problems respectively. Engineering Change Order (ECO) routing is frequently requested in the later design stage for the purpose of delay and noise optimization. ECO routing is very difficult as a result of huge existing obstacles and the requests for various design rules. Gridless routers are more applicable to overcome the problem barrier than grid routers. Therefore, we develop an efficient tile-based point-to-point router for the ECO routing of multi-million gate designs in this thesis.
Although tile-based routers have less number of nodes of routing graph than grid routers and connection-based routers, as the design complexity increases, the number of nodes of tile-based routing graphs have grown over thousand millions for SOC designs. We can reduce the complexity of tile-based routing graph to promote routing performance. In this thesis, we propose two methods to promote routing speed of the tile-based router. The first is Routing Graph Reduction. We propose two methods, i.e., redundant tiles removal and neighbor tiles alignment, to reduce the complexity of tile-based routing graph. It diminishes tile fragmentation as well as reduces the routing time without sacrificing routing quality. The second is ECO Global Routing. We propose different resource estimation scheme from that used by general global routing to reflect the characteristics of ECO routing problem. Also, we propose an ECO routing flow, including extended routing and GCell restructuring and rescheduling, to guarantee to find a feasible solution if there exists such a solution. By limiting the searching scope of ECO routing, ECO global routing improves a lot the routing speed at little expense of routing quality. Experimental results show that routing graph reduction can decrease the routing time by 40% and ECO global routing with routing graph reduction can further decrease the routing time up to 85% or so.
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