| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 93 === For deep-submicron and high-performance circuits, the interconnection delay plays a very important role in determining the circuit performance. In this thesis, we minimize final interconnections cost during the process of spare cell selection for functional change. We present a scheme which consists of three steps: matching, covering, and least-cost-first placement. It works in a sequential manner and integrates logic level data structures, physical cell location information, and fast useful heuristics to handle large scale ECO functional changed lists.
Unlike the traditional technology mapping that is based on the estimation of gate delays, area, and power, we apply modified dynamic programming algorithm in the covering step. Further, applying least-cost-first heuristic in different ways, we can evaluate the final interconnection cost of each ECO circuit tree more efficiently. Therefore, we can find a better implementation from various scheduling schemes. Experimental results show the efficiency and effectiveness of our algorithm.
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