Dynamically Reconfigurable Reed-Solomon Decoder IP Design Based on Unified Finite-Field Processing Element

• Main Authors: Jih-Chiang Yeo, 游志強
• Other Authors: 吳安宇
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/40651692359185275020

碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === Reed-Solomon (RS) codes play an important role in providing the error correction and the data integrity in various communication/storage applications. For high-speed applications, many RS decoders are implemented as dedicated ASICs based on parallel architectures, which can deliver high data throughput rate. For lower-speed applications, some RS decoders are implemented using fine-grained processing elements (PE) controlled by a programmable DSP core, which can provide high flexibility. Recently, the reconfigurable (RC) VLSI architectures become attractive since it can retain both flexibility and speed performance. In this thesis, based on a new coarse-grained PE, we develop the dynamically reconfigurable RS decoding architecture, which provides better flexibility and higher performance than ASIC-type and DSP-type designs, respectively. We propose the Multi-Symbol-Sliced (MSS) data-path structure, which supports the tradeoff between the data throughput rate and the power consumption. We design one m-PE architecture based on a coarse-grained unified finite-field Processing Element (PE). The m-PE architecture can be dynamically reconfigured to operate in 1-PE, 2-PE, …, m/2-PE and m-PE modes, which can support various requirements of the data throughput rate and the energy efficiency. In addition, by using the gated-clocking scheme, we can enhance the power saving greatly. We demonstrate a prototyping design using four processing elements, which can be dynamically reconfigured to operate in 1-PE, 2-PE and 4-PE mode with 140Mbps/18.91mW, 280Mbps/28.77mW and 560Mbps/48.47mW data throughput rate/power consumption, respectively.