Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics

碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === This thesis reports an analysis of intrinsic and fringing capacitance behavior in 100nm SOI (silicon on insulator) CMOS devices. In chapter 2, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with various oxide thickness...

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Main Authors: Yu-Sheng Lin, 林育生
Other Authors: 郭正邦
Format: Others
Language:zh-TW
Published: 2005
Online Access:http://ndltd.ncl.edu.tw/handle/71728309638341650656
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spelling ndltd-TW-093NTU054281062015-12-21T04:04:16Z http://ndltd.ncl.edu.tw/handle/71728309638341650656 Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics 考慮高介電係數閘極介電層之100奈米絕緣體上矽金氧半元件之電容分析 Yu-Sheng Lin 林育生 碩士 國立臺灣大學 電子工程學研究所 93 This thesis reports an analysis of intrinsic and fringing capacitance behavior in 100nm SOI (silicon on insulator) CMOS devices. In chapter 2, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with various oxide thicknesses. In chapter 3, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with high-k gate dielectric. With the same physical thickness or effective thickness, we compare it with conventional oxide. In chapter 4, we discuss the tunneling effect on capacitance behavior. With the same physical thickness or effective thickness, we report the tunneling phenomenon with various gate dielectrics. Chapter 5 is related to 2D device physics, we discuss FIBL(fringing-induced barrier lowering) in subthreshold region with various gate dielectrics, sidewalls, and drain voltages. 郭正邦 2005 學位論文 ; thesis 59 zh-TW
collection NDLTD
language zh-TW
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description 碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === This thesis reports an analysis of intrinsic and fringing capacitance behavior in 100nm SOI (silicon on insulator) CMOS devices. In chapter 2, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with various oxide thicknesses. In chapter 3, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with high-k gate dielectric. With the same physical thickness or effective thickness, we compare it with conventional oxide. In chapter 4, we discuss the tunneling effect on capacitance behavior. With the same physical thickness or effective thickness, we report the tunneling phenomenon with various gate dielectrics. Chapter 5 is related to 2D device physics, we discuss FIBL(fringing-induced barrier lowering) in subthreshold region with various gate dielectrics, sidewalls, and drain voltages.
author2 郭正邦
author_facet 郭正邦
Yu-Sheng Lin
林育生
author Yu-Sheng Lin
林育生
spellingShingle Yu-Sheng Lin
林育生
Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics
author_sort Yu-Sheng Lin
title Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics
title_short Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics
title_full Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics
title_fullStr Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics
title_full_unstemmed Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics
title_sort analysis of capacitance behavior in 100 nm soi cmos vlsi devices with high-k gate dielectrics
publishDate 2005
url http://ndltd.ncl.edu.tw/handle/71728309638341650656
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