Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics
碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === This thesis reports an analysis of intrinsic and fringing capacitance behavior in 100nm SOI (silicon on insulator) CMOS devices. In chapter 2, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with various oxide thickness...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/71728309638341650656 |