DUAL-LOOP CLOCK AND DATA RECOVERY CIRCUIT FOR OC-192

• Main Authors: Kuo-Cheng Tseng, 曾國城
• Other Authors: Shu-Chuan Huang
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/03696143338108306161

碩士 === 大同大學 === 通訊工程研究所 === 93 === As the rapid growth of the volume of the internet data, it is necessary to increase the speed of the media. The optical communication system can accommodate large volumes of data across a long distance. For example, in the optical communication system standards, OC-48 transmission rate is 2.488 Gb/s, and OC-192 reaches 9.953 Gb/s, etc. The design of the clock and data recovery (CDR) system is a challenging part when implementing an optical receiver. Due to the high transmission frequency, traditionally GaAs, BJT, or BiCMOS process is used to design the circuit. However, the disadvantages are expensive, high power dissipation, and not easy to integrate. In contrast, CMOS process technology provides low cost, low power dissipation, and easy to integrate. This research focuses on the design of the CMOS CDR for optical system (OC-192), where TSMC 0.18μm CMOS 1P6M process is used for the simulation. In order to overcome the problem of frequency acquisition, we utilize CDR architecture in dual loops, including the phase detector and frequency acquisition device. Agilent EEsoft EDA-ADS is used for circuit simulation and HSPICE for post-simulation of CMU. The power consumption of the voltage control oscillator (VCO) is only 3.78mW from a single 1.8V supply and the phase noise is -111dBc/Hz at 1 MHz offset. The CDR has a bandwidth of 2.2MHz for a 622MHz reference and the acquisition time is about 4.8μs. The total power consumption for the CDR is 86.25 mW.