Application of Drum-Buffer-Rope to the Capacity Planning of Wafer Fabrication with Time Constraint
碩士 === 中原大學 === 工業工程研究所 === 94 === Time constraint is applied after the cleaning and banking process to avoid wafer contamination in semiconductor manufacturing. Any lot failing to meet the time constraint needs to be reworked. Therefore, it is important to control the work-in-process (WIP) level t...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44851783407599461769 |
| Summary: | 碩士 === 中原大學 === 工業工程研究所 === 94 === Time constraint is applied after the cleaning and banking process to avoid wafer contamination in semiconductor manufacturing. Any lot failing to meet the time constraint needs to be reworked. Therefore, it is important to control the work-in-process (WIP) level to reduce the number of lots whose waiting time exceeds the time constraint. From the viewpoint of Theory of Constraints (TOC), bottleneck machine governs the system throughput. Therefore, it is critical to control the WIP level in front of the bottleneck machine in the process with time constraint requirement.
This research develops a capacity planning system (CPS) for the backend process of semiconductor manufacturing with reentrant process. CPS applies TOC to manage time constraint, so lot rework and capacity loss can be minimized. CPS determines the expected WIP level using TOC’s Drum-Buffer-Rope mechanism and then controls wafer release to meet the expected WIP level. The best combination of WIP level and time constraint is identified by simulation study and response surface analysis. Simulation results reveal that CPS can significantly reduce lot rework and capacity loss in different production scenarios.
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