A Study of Drive Current Enhancement Methods and Related Reliability Issues for MOSFETs

• Main Authors: Chia-Yu Lu, 呂嘉裕
• Other Authors: Horng-Chih Lin
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/33162682263092973012

博士 === 國立交通大學 === 電子工程系所 === 94 === In this thesis, we have investigated the impacts of silicon nitride (SiN) capping layer on drive current and the associated reliability issues. In addition, novel SOI devices were also fabricated and characterized in this study. This study includes the fabrication and characterization of devices with poly-SiGe gate electrode. Attentions were paid on the drive current and NBTI degradation of PMOSFETs with poly-SiGe gate and PE-SiN capping layer. Moreover, NMOSFETs with LP-SiN capping were also fabricated and investigated. Bandgap narrowing effect induced by local strain and lateral diffusion of interface states after hot-carrier stress were addressed. Finally, novel Schottky-barrier (SB) FinFET with impurity segregation and UTB SOI devices with CMP-free and gate-last process were fabricated and characterized. Devices with poly-SiGe gate electrodes can help alleviate poly-depletion and boron penetration problems due to higher dopant activation in p-type semiconductor. These result in about 5.8% enhancement of saturation current as compared with the poly-Si-gated counterparts. During NBTI stress, devices with poly-SiGe gate even have longer lifetime than those with conventional poly-Si gate. Next, poly-SiGe-gated PMOSFETs with local compressive strain in the channel induced by a compressive PECVD SiN capping layer were fabricated in this study. The drive current of PMOSFETs is found to be significantly enhanced by the incorporation of the compressive PE-SiN capping layer. Specifically, the drive current enhancement can reach about 29% and 36% for devices with PE-SiN capping thickness of 100 nm and 300 nm, respectively, at a channel length of 0.45 mm. Despite this much-coveted merit, our results also show that the PE-SiN capping may aggravate the NBTI characteristics. The abundant hydrogen species contained in the PE-SiN layer as well as the strain energy stored in the channel may be the culprits for the worsened reliability. Cares should therefore be exercised to optimize the amount of hydrogen species to ensure that the NBTI effect is kept at bay, while simultaneously maintaining the performance enhancement pertaining to the compressive strain channel. In addition, the saturation phenomena in DVth and DNit are also observed during NBTI stress. This is believed to be due to the fact that nearly all the interfacial Si-H bonds have been broken. DNBTI and AC stressing were also performed on PMOSFETs with PE-SiN capping layer. The results show that devices with SiN capping have larger recovery of DVth and DNit than those without capping. The neutral hydrogen species are mainly responsible for the recovery phenomena of the generated interface states in the SiN-capped devices. However, a strong dependence on the AC stress frequency is also observed for the SiN-capped devices. Our observation reveals an important message that the aggravated NBTI in the SiN-capped devices could be largely alleviated by high frequency operation. In this study, we have also investigated the effects of LPCVD SiN capping process and the resultant channel strain induced by the SiN-capping layer on the device characteristics. Enhancement ratio up to 20% is achieved for devices with LP-SiN capping thickness of 300 nm at a channel length of 0.4 mm. The bandgap narrowing effect due to the channel strain may result in further lowering in Vth as the channel length is shortened. Our results indicate that the thermal budget associated with the deposition of the SiN capping layer could alleviate the reverse short-channel effect seen in the uncapped devices. However, it is also the main culprit for the gate dopant out-diffusion and gate oxide thickness variation. The gate oxide thickness extracted by F-N tunneling current would increase from 2.705nm for the control sample to 2.85nm for the 300nm-SiN-capped sample. In addition, interface state density is also affected by SiN capping procedure. More hydrogen species are expected to participate in interface state passivation as the duration of the LP-SiN deposition increases. Next, both the deposited LP-SiN layer and/or the deposition process itself have significant impacts on the device operation and the associated reliability characteristics. In fact, the accompanying bandgap narrowing and the increase in carrier mobility tend to worsen the hot-electron reliability in the LP-SiN-capped devices. Nevertheless, attentions should also be paid to the SiN deposition process itself. Owing to the use of hydrogen-containing precursors, abundant hydrogen species is incorporated in the oxide that may also contribute to the hot-electron degradation. The edge effect of hot carrier stress is also a factor to cause reliability degradation in SiN-removal devices. In addition, the hot carrier degradation of devices with SiN capping is independent of SiN thickness due to gate oxide thickness variation and bandgap narrowing induced by channel strain. Finally, we have successfully demonstrated Schottky barrier (SB) FinFETs formed by Pt salicide and impurity segregation. By adjusting SB height through impurity segregation, excellent device performance is achieved without resorting to field-induced drain (FID) structure to reduce the leakage current. The driving current can even be five times larger than that of the SB device with FID. Moreover, we have also proposed and successfully demonstrated a new CMP-free process for fabricating UTB SOI PMOS transistors with SiGe raised source/drain and replacement gate schemes. Satisfactory device characteristics have been achieved. With its inherent gate-last feature, the new scheme lends itself handily to the advanced nano CMOS featuring high-k gate dielectric and metal electrode.