| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 94 === The back-end-of-line (BEOL) RC delay has gradually become a major limiting factor in circuit performance as a result of the rapid shrinking of critical dimensions. With reduced resistivities and dielectric constants, the metallization system for the interconnect structures has shifted from Al(Cu)/oxide to copper/low-k dielectrics. However, Cu interconnects still pose a reliability concern due to electromigration-induced failure over time. The rapid decrease in Cu conductor dimensions while maintaining a high current capability and a high reliability has emerged as a serious challenge.
The objective of this dissertation is to investigate the characteristics and failure mechanism involved in Cu electromigration. Chapter 1 gives an introduction to the topic and discusses the background to study. Chapter 2 describes electromigration testing and analysis techniques in detail, and is intended to help familiarize the reader with the experimental aspects of this work in order to create a basis of understanding for the results sections that follow. In Chapter 3, first of all, Cu interconnect electromigration is examined using three low-k materials (k= 2.65 ~ 3.6) in a variety of structures. A number of test structures were designed to identify the EM failure modes and the weak links in the interconnect system. A strong dependence on current direction in the electromigration lifetime of three-level via-terminated metal lines was shown. Moreover, individual processing approaches lead to distinct EM behaviors and related failure modes. Multimodality in the electromigration behavior of Cu dual-damascene interconnects was studied. Both superposition and weak-link models were used for the statistical determination of the lifetimes of each failure model (statistical method). Results correlated to the lifetimes of the respective failure models physically identified according to resistance time evolution behavior (physical method). A excellent agreement was achieved.
Based on the above understanding, the weak links of interconnect system were identified.Chapter 4 describes the correlation between the electromigration lifetime and the Cu surface cap-layer process. An especially suitable EM test structure was designed to evaluate the properties of the Cu cap-layer interface. A significant improvement in electromigration lifetime is achieved through modification of the pre-clean step before the deposition of the cap-layer and by changing the Cu cap/dielectric materials. A possible mechanism for the enhancement of EM lifetime was proposed. A Cu-silicide formation prior to cap-layer deposition and the adhesion of the Cu/cap interface were found to be the critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to the electromigration MTF and the activation energy.
Chapter 5 outlines the effects of width scaling and layout variation on dual-damascene Cu interconnect electromigration. Electromigration versus line width in the 0.12—10 um range and the configuration of the via/line contact has been investigated. There are two scenarios that cover the impact of width scaling on electromigration. One is the width <1 um region, in which the MTF shows a weak width dependence, except under the via-limited conditions. The other is the width >1 um region, in which the MTF shows a strong width dependence. A theory was proposed to explain the observed behavior. For polycrystalline lines (width >1 um), the dominant diffusion paths are a mixture of grain boundary and surface diffusion. The activation energy for the dominant grain boundary transport (width >1 um) is approximately 0.2 eV higher than that of the surface and grain-boundary transport (width ~ 1 um). The derived activation energies for both grain-boundary and surface diffusion are obtained from the Cu drift velocity under EM stressing. The activation energy data obtained from both the measured and derived methods for both the surface and grain-boundary transport were found to be compatible. The mechanisms governing the EM lifetime of interconnects leads to the identification of via interconnect design rules for maximizing electromigration lifetime.
In Chapter 6, the electromigration short-length effect is investigated through experiments on lines of various lengths (L), being stressed at a variety of current densities (j), and using a technologically realistic three-level structure. This investigation represents a complete study of the short-length effect following the development of an enhanced dual-damascene Cu process. Lifetime measurement and resistance degradation as a function of time were used to describe this phenomenon. A simplified equation is proposed to analyze the experimental data from various combinations of current density and line length at a certain temperature. The resulting threshold–length product (jL)C value appears to be temperature dependent, decreasing with an increase in temperature in a range of 250oC to 300oC.
Finally, Chapter 7 summarizes the results of the study and outlines some potential future directions for research into the interconnect electromigration reliability field. The multimodality distributions in various Cu/low-k processes are fitted using various bimodal methods to obtain precise lifetime values. Methods of optimizing the Cu electromigration performance have been investigated through Cap/dielectric interface re-engineering. Geometric variations of the test structure, including width scaling, length scaling, and vai/line configuration effects, were investigated to reveal the characteristics of Cu electromigration. A possible model is proposed to explain the electromigration behavior, and provides the means to ensure future design-in reliability. Much insight into electromigration failure modes and characteristics has been gained through experimentation using Cu dual-damascene technology to identify its distinctive behaviors.
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