Diagnosable Design of SoC Testing Architecture IEEE P1500

• Main Authors: Chih-Ling Yang, 楊智鈴
• Other Authors: Hsin-Chou Chi
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/56858360201004541275

碩士 === 國立東華大學 === 資訊工程學系 === 94 === IEEE P1500 has been proposed as a standard and applied widely for system-on-chip (SoC) testing. However, in order to enhance the accuracy of SoC testing, IEEE P1500 must be tested and diagnosed before using it. This thesis analyzes the behaviors of IEEE P1500 and then proposes a design-for-diagnosability (DFD) architecture for IEEE P1500. We present our efficient diagnosis schemes and describe how to locate the fault position based on our schemes. In this design, the diagnostic schemes are realized with adding extra hardware with limited complexity. These schemes can handle both single stuck-at fault and hold-time fault. The fault location can be identified based on the response sequence of the output. It only requires a small hardware overhead. The schemes for two main components of IEEE P1500, WIR and WBR, can diagnose the circuits for single stuck-at fault and hold-time fault efficiently.