Design and Implementation of All-Digital Fast-Locked DLL-Based Clock Generators
碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === To minimize timing skews and jitters of the clock signals, Delay-locked loops (DLLs) have been widely used. The DLLs benefit from the unconditional stability, fast locking process and better jitter performance compared with the PLLs. However, various intrinsic p...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/57613998803275086961 |