| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === As the complexity of SoC systems is increasing, it is hard to interconnect a variety of IPs. OCN (On-Chip Networking) system is a new method to solve the chip communication problems. Based upon pre-defined components and architecture, we can build a high performance and reliable communication environment. Currently, OCN system adopts simple or fixed architectures, such as star and mesh. However, these architectures may cause inefficient bandwidth usage and high hardware cost. Therefore, analytical decision and performance evaluation for OCN system are important issues before implementation.
The goal of this thesis is to map SoC to OCN and optimize the hardware cost. We propose an application-aware design flow and approaches, called AMAP. Due to the differences between SoC Applications, we analyze the requirements of SoC applications. In view of that deciding the location of each IP on OCN system is very important, we propose binomial mapping algorithm to get a fast and efficient 2D-mesh topology. According to the traffic load after mapping, we propose several approaches to optimize the hardware cost and improve the OCN utilization. By using the proposed binomial mapping algorithm, we can save 37% traffic load and 46% Hop. Moreover, we can save 75~87.5% hardware cost by the optimization approaches under bandwidth constraints. Furthermore, the OCN architecture is successfully verified on established infrastructure, CoWare ConvergenSC and FPGA platform.
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