Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
碩士 === 淡江大學 === 電機工程學系碩士班 === 94 === Test access mechanism (TAM) and test schedule for System-On-chip (SOC) are challenging problems. Test schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a core section method based on generalized 2-D r...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28373486515997039599 |