A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system

碩士 === 中華大學 === 電機工程學系(所) === 95 === This paper proposes a 10-bit, 40MS/s CMOS pipelined analog-to-digital converter (ADC) which applied to IEEE 802.11a Wireless LAN (WLAN) communication system. We discuss the structures and components of the proposed pipelined ADC operating at a 3.3V supply voltage...

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Main Authors:	Tzu Yen Hsu, 徐梓嚴
Other Authors:	Ching-Cheng Tien
Format:	Others
Language:	zh-TW
Published:	2007
Online Access:	http://ndltd.ncl.edu.tw/handle/98392786387006611954

id	ndltd-TW-095CHPI5442011
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spelling	ndltd-TW-095CHPI54420112016-05-18T04:12:22Z http://ndltd.ncl.edu.tw/handle/98392786387006611954 A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system 應用於IEEE802.11aWLAN之類比數位轉換器 Tzu Yen Hsu 徐梓嚴碩士中華大學電機工程學系(所) 95 This paper proposes a 10-bit, 40MS/s CMOS pipelined analog-to-digital converter (ADC) which applied to IEEE 802.11a Wireless LAN (WLAN) communication system. We discuss the structures and components of the proposed pipelined ADC operating at a 3.3V supply voltage which is implemented in TSMC 0.18μm CMOS process. Owing to using Switched-capacitor Common Mode Feedback and Digital-Error-Correction technique, we design this ADC by using less-sensitive fully-differential dynamic comparator. The great merits are no static power consumption and better noise-immunity. Operational Transduction Amplifier (OTA) consumes only 7mW. The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.34 dB with a full-scale sinusoidal input at 1MHz. Ching-Cheng Tien 田慶誠 2007 學位論文 ; thesis 103 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 中華大學 === 電機工程學系(所) === 95 === This paper proposes a 10-bit, 40MS/s CMOS pipelined analog-to-digital converter (ADC) which applied to IEEE 802.11a Wireless LAN (WLAN) communication system. We discuss the structures and components of the proposed pipelined ADC operating at a 3.3V supply voltage which is implemented in TSMC 0.18μm CMOS process. Owing to using Switched-capacitor Common Mode Feedback and Digital-Error-Correction technique, we design this ADC by using less-sensitive fully-differential dynamic comparator. The great merits are no static power consumption and better noise-immunity. Operational Transduction Amplifier (OTA) consumes only 7mW. The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.34 dB with a full-scale sinusoidal input at 1MHz.
author2	Ching-Cheng Tien
author_facet	Ching-Cheng Tien Tzu Yen Hsu 徐梓嚴
author	Tzu Yen Hsu 徐梓嚴
spellingShingle	Tzu Yen Hsu 徐梓嚴 A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system
author_sort	Tzu Yen Hsu
title	A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system
title_short	A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system
title_full	A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system
title_fullStr	A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system
title_full_unstemmed	A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system
title_sort	design of analog-to-digital converter for ieee 802.11a wlan system
publishDate	2007
url	http://ndltd.ncl.edu.tw/handle/98392786387006611954
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A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system

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