| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === Electronic image-sensing device currently comprises CCD (charge-coupled device) and CMOS (complementary metal-oxide-semiconductor) technology, while the tendency towards low power consumption and system-on-chip (SOC) integration led by the market makes CMOS image sensor stand out conspicuously in related fields and obtain a major stance gradually, substituting for CCD image sensor; however, the noises and limitations influenced by characteristics of transistors result in the lack of dynamic range close to the one of human eyes be implemented in this kind of image sensor, and in order to broaden the scope of several applications, high dynamic range image sensor becomes a subject under research and development.
As a result of the above phenomenon, this thesis would like to take dynamic range of a CMOS image sensor as the research goal. At the beginning, the dynamic range characteristics of CMOS image sensor would be realized, followed by introducing pixel cell modification plans in an analog design perspective toward the shortcomings of dynamic range increment in present techniques through the usage of double photodiodes, a technique of releasing charges and an implementation of a self variable capacitor, totally three kinds of methods and the decision of proposed chip’s parameters is then determined by circuit simulation. The chip is produced after completion of circuits’ layout in the end and the verification is done by measurement of complete chip to check its practicability. An increment of 7 to 17dB in dynamic range is obtained through measurement and there is not any additional power consumption needed for its achievement, thus further efficiency and practicability for the whole circuits could be a future plan.
The proposed chip, with a die area of 1.193×0.813 mm2, is patronized by National Applied Research Laboratories National Chip Implementation Center (NARL NCIC), accomplished by using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm 1P6M 3.3V mixed-signal CMOS process. Pixel arrays adopt 3-T active pixel sensor (APS) and photodiode which composed of NW/Psub junction and include three types of design that used for gathering the reference data needed for analysis by increasing different parameter combination in the chip.
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