| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === This test chip is used feedback mechanism to realize a frequency output CMOS image sensor with adaptive dynamic range. The full chip consists of 64 64 pixel arrays, column processing circuits, column and row shift register, biasing circuit and digital buffer. And column processing circuits comprise comparator, D flip-flop, an eight bits counter and memory. This structure characters the adaptive dynamic range by adjusting the reference voltage of comparator or readout time of one-row pixel. Simulation results show that the dynamic range of the sensor is 78dB originally and achieves to 100dB in high illumination after adjusting parameters. It can extend dynamic range of 22dB.
This sensor adopts 3T-like pixel which has extra two transistors to improve the conversion gain of pixel and achieve higher precision in readout. Furthermore, the digital control signal is generated by FPGA. It not only has larger flexibility in test but also reduce the circuit complexity.
The test chip is fabricated in TSMC 0.35μm 2P4M 3.3V mixed-mode process and occupies the area of 1.684×1.641 mm2. Each pixel adopts N-well/P-sub photodiode and measures the area of and fill-factor of 38.6%.
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