| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 95 === Pipelined analog-to-digital converters (ADCs) have intrinsic high-speed
characteristics and are commonly used in wideband communication and video
systems. However, with the higher resolution and throughput rate the power
consumption and the required area are getting larger. Therefore, the double-sampling
technique provides a method applied to the pipelined ADC to duplicate the sampling
rate without consuming two times of power and area.
The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was
simulated by TSMC 0.18um 1P6M CMOS process. It consists of one front-end SHA,
eight cascaded 1.5-bit stages, and a final 2-bit flash converter in the last stage. All
analog circuits are fully differential with a 2Vpp input signal and 1.8V power supply.
The operation amplifier in each stage is shared between the two paths and active for
one of both paths alternately. Not only the operation amplifier in each stage is shared,
but sub-ADC is common to both paths. As a result, it makes sampling more efficient
and increases the throughput rate of the pipelined ADC.
The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was
finally implemented by TSMC 0.18um 1P6M CMOS process. The pipelined ADC
dissipates 103mW at a 100MHz clock rate and a 200MS/s sampling rate with 1.8V
supply voltage. The chip area is 1.134*1.380 mm2. The simulated differential
nonlinearity (DNL) and integral nonlinearity (INL) are ±0.75 LSB and ±0.95 LSB,
respectively. And the peak SNDR about 56dB for an input signal of 1MHz sine wave.
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