VariTamer: A Heterogeneous Platform for Deciding the Best Layout Placement in Physical Implementation
碩士 === 國立中央大學 === 電機工程研究所 === 95 === While MOS transistors continuously scale down in technologies below 90 nano-meter, they bring along larger parameter variability. Analog EDA is needed increasingly important in future SoC design. The parameter variation of all transistors should have certain corr...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/18259054408943546558 |