Statistical Evaluation of Transmission Quality for Digital Logic Circuits
碩士 === 國立中央大學 === 電機工程研究所 === 95 === As the frequency of digital logic circuit rises up, the influence of jitter and skew on the signal is getting more serious. In this thesis we build a model based on a D flip-flop chain and use a statistical method to evaluate the transmission quality of digital l...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92366989733948859420 |