A 70-500 MHz 50% Duty-Cycle Correction Circuit with a Frequency-Domain Measurement Technique in 0.35-μm CMOS
碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === A 50% duty-cycle correction (DCC) circuit is reported in this thesis. The proposed DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output whose pulse width is adjusted to half of...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/43091014053269275843 |