Design and Implementation of an Area Aware H.264 Encoder

• Main Authors: Chia-Wen Tsai, 蔡嘉文
• Other Authors: Sao-Jie Chen
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/75815182727612207888

碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === H.264/AVC is one of the latest international video coding standards. This standard is developed by the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. It can achieve higher coding efficiency than previous standards. With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC) are increasing. However, AVC requires a much higher computation complexity due to the use of coding tools such as variable block sizes motion estimation (VBSME). This makes the pure software solution nearly impossible to work even under low requirement. In this Thesis, we design and implement an area aware H.264 encoder architecture including full search motion estimation, intra prediction, forward and inverse transforms, and forward and inverse quantizations. Many works were done with the consideration of saving area, such as the choice of architectures and the schedule of processes. After combining all these modules, the system can encoder a QCIF picture in 7.13K clocks. After carefully checking the correctness of design, the prototype of the proposed design was implemented in TSMC 0.18μm 1P6M process technology and fabricated by CIC. The maximum operation frequency of the system is 108MHz. The core size of the chip is 2mm x 2mm with a total gate count about 410K and the die size is 2.95mm x 2.95mm after placement and routing.