Simulation of 0.18um Process and Ion Implant for Zener Diode Design

• Main Author: 陳耀文
• Other Authors: 李元彪
• Format: Others
• Language: zh-TW
• Online Access: http://ndltd.ncl.edu.tw/handle/64481038602168704490

碩士 === 建國科技大學 === 電機工程系暨研究所 === 96 === This research is the Zener Diode design by standard CMOS 0.18m fabricated processes. Only added or modified part of standard processes, the standardized processes could involve the common used Zener Diode, so the SoC(System on one Chip) contains various Zener Diodes. By the way of Tsuprem4 and Medici simulations, the implant processes are suggested to be improved in order to change the breakdown voltage and to design Zener Diode. Here, additional two processes are recommended to make it achieve the common styles. There are two steps to improve it. Firstly, a new Phosphor implant cooperates with the original N-HDD implant. Secondly, a new Arsenic implant works with the original P-Well implant. Therefore, the standard processes could be built in various styles Zener Diodes.