Block-Based Built-In Self-Repair Architectures for Content-Addressable Memories
碩士 === 輔仁大學 === 電子工程學系 === 96 === This paper describes BIST and repair architectures for content-addressable memories. With our proposed architectures, the CAM array is divided into column banks and row banks. If the CAM array contains both column banks and row banks, the overlapped area of a column...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/58298523550601736902 |
| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 96 === This paper describes BIST and repair architectures for content-addressable memories. With our proposed architectures, the CAM array is divided into column banks and row banks. If the CAM array contains both column banks and row banks, the overlapped area of a column bank and a row bank is called a divided array. Each row of a row bank is defined as a row block. Redundant rows are also divided into redundant row blocks which repair faulty row blocks for each divided array. Each divided array of the CAM array has its corresponding word-line and match-line steering circuits to replace the faulty row blocks. We also improve the word-line and match-line steering circuits such that each divided array can be repaired by two redundant row blocks. By dividing the CAM array, the number of redundant row blocks can be increased to repair more faulty row blocks. The repair rate can achieve up to 74.35% for column bank = 4 and row bank = 2. In order to verify our design, we follow the cell-based design flow to implement our circuit. The CAM memory size of our implementation is 32 × 64 bits. The size of the redundancy is 8 × 32-bits. The operating frequency is about to 25 MHz.
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