| Summary: | 碩士 === 國立成功大學 === 電機工程學系專班 === 96 === The continuous CMOS scaling has resulted in a continuous improving of the speed, power consumption, packing density and performance of integrated circuits. As the process technology becomes attractive for the 45 nm node and beyond, the equivalent oxide thickness (EOT) of the gate dielectrics oxide layer will be down to 1.1 nm or even thinner. It is quite obvious that the gate leakage current will be higher and CMOS circuit will fail, using the SiO2 in next process generation. Various insulators with high-permittivity (high-κ) have been proposed and investigated to serve as alternative to SiO2 toward CMOS technology of next generation.
In this study, we present a computationally efficient model to calculate the direct tunneling current from an inverted p-type (100) Si substrate through interfacial SiO2 and high-κ gate stacks. Four main physical conditions were considering : the total inversion layer charge density, the average inversion charge centroid thickness, the electron impact frequency on the interface, and the carriers tunneling probability. This model consists of quantum mechanical calculations for the inversion layer charge density and a modified WKB approximation for the transmission probability. The modeled direct tunneling currents agree well with a self-consistent model and experiment data, suggestion that the direct tunneling current is main domination of the gate leakage current in the low electrical field condition. For the same effective oxide thickness (EOT) of 1.5 nm, the direct tunneling current of a HfO2 high-κ dielectric (4.8 nm, κ ~25) overlaying a 0.7 nm thermal oxide is reduced about 4~5 order magnitude compared with a pure SiO2 film of the same EOT at low gate voltage. The effects of interfacial oxide thickness, dielectric constant and barrier height on the direct tunneling current have also been studied as a function of gate voltage.
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