1.8V Clock and Data Recovery with Full Linear Control Range VCO
碩士 === 國立暨南國際大學 === 電機工程學系 === 97 === Clock and data recovery (CDR) circuit plays an important role in the receivers of communication applications. In recent years, high data rate and low power consumption become the main research issues of CDR. In this thesis, we proposed a 1.8V 1.25Gbps full rate...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74030495527803348965 |