On Minimizing Substrate Noise and Meeting Symmetry Constraint in Mixed-Signal SoC Floorplan Design

• Main Authors: Chung-Hsin Lin, 林忠信
• Other Authors: Sheng-Fuu Lin
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/50083128610336677798

碩士 === 國立交通大學 === 電機學院碩士在職專班電機與控制組 === 96 === In recent years, in order to handle substrate noise and process variation in high-end mixed-signal circuit, analog circuits are often required placement symmetrically to the axis, and high noise digital circuits need to far aware form noise interference to analog blocks. In floorplan process, for the symmetry components of the analog circuits, we propose a simple and efficient method to obtain the closest blocks placement of the analog cells of the some symmetry groups satisfying the symmetry constraints, and handle the digital blocks of high noise interference to analog blocks by using substrate noise model. We apply sequence-pair and LCS (Longest Common Subsequence) algorithm to implement the floorplan. In order to obtain solutions effectively, the analog blocks and digital blocks are implemented by two-phase method separately. In first phase, to execute the simulated annealing with the positions of the symmetry groups and non-symmetry blocks, and in second phase to achieve a floorplan with minimize digital blocks noise interference to analog blocks. Then we compare our experiment results to the papers with symmetry constraints and mixed-signal SOC (System-On Chip) floorplan with minimize substrate noise recently, and demonstrate the effectiveness of our approach by experiment result.