An Automatic Core-based Delay Test SoC Integrator Based on IEEE Std.1500
碩士 === 國立清華大學 === 電機工程學系 === 96 === Due to the rapidly increasing capacity of semi-conductor technology, the design methodology has come to a higher level of abstraction. The IEEE 1500 is provided to test functionality of each core in SoC but dose not verify its timing specification. In this thesis,...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16368252604995707059 |