| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 96 === Due to the rapidly increasing capacity of semi-conductor technology, the design methodology has come to a higher level of abstraction. The IEEE 1500 is provided to test functionality of each core in SoC but dose not verify its timing specification. In this thesis, a delay fault test architecture that consists of modified wrappers within a delay-test-aware clock controller based on IEEE 1500, the modified TAP controller and a daisy-chained TAM bus architecture are presented. Besides, an automatic program for generating whole test architecture and a chip level testbench for delay fault testing of cores both stored in Verilog files is proposed. In this way, delay fault testing of cores in core-based SoC design is controlled easily and efficiently.
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