Design and Implementation of a Low-Power IEEE 802.16e LDPC Decoder by Utilizing Decoding Operation Reduction Algorithm
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 96 === For the emergency of low power consumption demand in mobile applications, a decoding operation reduction algorithm for Low-Density Parity Check (LDPC) codes is proposed. Our operation reduction layered decoding algorithm reduces active node computation to lower...
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37210431522138099854 |
| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 96 === For the emergency of low power consumption demand in mobile applications, a decoding operation reduction algorithm for Low-Density Parity Check (LDPC) codes is proposed. Our operation reduction layered decoding algorithm reduces active node computation to lower LDPC decoder power consumption. Layered nodes are periodically refreshed to minimize coding gain degradation. Besides, two variation algorithms are also explored. Low hardware overhead partially parallel LDPC decoder architecture for all three decoding operation reduction algorithms is also described. Simulation results show that our algorithm reduces the number the most power consuming memory access operation up to 75% compared to the original layered decoding. The FPGA implementation results show that our architecture only add 0.6% hardware cost and the throughput is up to 67~292Mbps at frequency 140MHz.
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