Clock and Data Recovery Circuit with Improved Half-Rate Linear Phase Detector

• Main Authors: Chun-Yung Cho, 卓均勇
• Other Authors: 曹恆偉
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/28681929076217453132

碩士 === 臺灣大學 === 電子工程學研究所 === 96 === In this thesis, we will introduce general clock and data recovery (CDR) circuit architectures and describe the building blocks including phase detector, voltage control oscillator, and frequency detector. And the operation principles of each building block will be mention. The loop characteristics of CDR will also be discussed, including noise response, linear type loop characteristic, and non-linear type loop characteristic. This thesis presents an improved half-rate linear phase detector for a clock and data recovery circuit. The phase detector can retime the full rate data by itself, eliminating the need for decision circuit and the timing issues of it. The pulse widths of the up and dn output pulses are the same at phase lock, which many half-rate linear operations are faced with charge pump current scaling issues. Hogge type phase detector timing compensation is discussed. We proposed a dual-band linear clock and data recovery circuit without a local reference clock. A half rate frequency detector is used to increase the capture range without disturbing the control voltage at phase lock. A dual-band voltage control oscillator (VCO) is also presented to widen the VCO operation range and to reduce the VCO conversion gain. The proposed CDR can operate at 1.62Gbps (low) and 2.7Gbps (high) input data rates. The low speed retimed data jitters are 73.4 ps (p-p) and 13.5 ps (rms). The high speed retimed data jitters are 87 ps (p-p) and 16 ps (rms). The bit error rate is less than 10-12. This chip is fabricated in 0.18- m 1P6M CMOS technology in an area of 750μm×750μm: the core area is 600μm×600μm, and the power dissipation excluding output buffer is 50 mW from a 1.8V supply.