FPGA Implementation of a Sinusoidal JitterMeasurement Technique
碩士 === 臺灣大學 === 電機工程學研究所 === 96 === This study is to implement an on-chip sinusoidal jitter testing technique for design for test (DfT) application. The proposed technique utilizes cumulative density function (CDF) based method to track the sinusoidal jitter, and applies post processing to enhance t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/35873996799780096160 |