Surge Current Minimization of Power Gated Circuits in High Level Synthesis

• Main Authors: Jheng-Fu Yeh, 葉烝輔
• Other Authors: Shih-Hsu Huang
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/29657433873240249935

碩士 === 中原大學 === 電子工程研究所 === 97 === Nowdays, the process technology is scaling from deep sub-micron tonano-meter regime, it is important to reduce leakage power. Among various methods, the power gating is the most effective technique to reduce the leakage power. Thus, we use the power gated circuits to reduce the leakage power of an idle function unit. However, when the functional unit is turned on, a sudden discharge called surge current, is induced. If too many functional units are turned on simultaneously, the instantaneous accumulated surge current may lead to the malfunction of the circuit. In order to solve this problem, in this thesis, we point out the high-level synthesis (include operation scheduling and functional unit binding) has a great impact on the maximum surge current. In addition, under the same leakage power constraint, we discover that the different high-level synthesis results lead to different maximum surge currents. Then, based on that observation, we propose two mixed-integer linear programs (MILP): one MILP to formally draw up the surge current minimization problem, and the other one MILP to formally draw up the leakage-power-driven surge current minimization problem. Compared with the existing design flow, benchmark data show that our approach can significantly reduce the maximum surge current without any design overhead.