| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 97 === To avoid wasting man power and design time, layout migration plays an important role in the re-design of a cell library and full-custom block. Traditional layout migration suffers the disadvantage of shape distortion of objects and destruction to topology between objects. It may alter the features produced by original layout topology and also makes the migrated layout hard to be recognized and verified by designers. In nanometer processes, via has been one of important factors to cause manufacturing defect. For this critical problem, foundries suggested IC designers using redundant via to connect metal wires on different layers. This thesis based on the previous work. Additionally, the space in specific area was preserved for redundant contacts and vias. The migration flow contains Y-direction linear programming base redundant contact and via aware migration and X-direction constraint graph base redundant contact aware migration. Experimental results show that about 40% improvement of failure rate for benchmark circuits implemented by our cell library is achieved without extra cost in total cell area, on the other hand the timing difference of the our cells and the cells without considering redundant contact and via is at most 2%. On the other hand, the number of redundant contacts can be traded of against cell area under the proposed cost.
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