Tolerating Load Miss Latency by Extending Effective Instruction Window with Low Complexity
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 97 === The confliction between increasing the instruction window size and keeping the clock cycle time small is getting worse. The run-ahead execution eases this problem by exploring higher memory level parallelism (MLP). However, the execution results produced in th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/51616704233650444721 |