Voltage Island-aware Floorplanning for SoC design
碩士 === 國立清華大學 === 資訊工程學系 === 97 === Reducing power consumption is an significant issue in modern System-on-Chip designs. Multiple-supply voltages (MSV's) design is one of the effective ways for dynamic power reduction, and floorplanning is the appropriate stage in the physical design cycle for...
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ndltd-TW-097NTHU53920902015-11-13T04:08:49Z http://ndltd.ncl.edu.tw/handle/32082571594069564724 Voltage Island-aware Floorplanning for SoC design 系統單晶片下考量電壓島佈局的平面規劃 Tang, Chih-Chieh 唐志傑 碩士 國立清華大學 資訊工程學系 97 Reducing power consumption is an significant issue in modern System-on-Chip designs. Multiple-supply voltages (MSV's) design is one of the effective ways for dynamic power reduction, and floorplanning is the appropriate stage in the physical design cycle for applying MSV's design. Previous works have addressed the MSV's design problem at floorplanning stage by solving the voltage assignment problem and the floorplanning problem separately. In this thesis, we propose a simulated annealing (SA) based voltage island-aware floorplanning algorithm to solve the two problems simultaneously. Our algorithm is based on corner block list [1] which is efficient for integrating the evaluation process of power costs function into SA. Experimental results show that our algorithm could save 31.63\% total power consumption by forming three voltage islands in average. We could obtain better deadspace, total wirelength and power consumption than the previous work [2] as well. Mak, Wai-Kei 麥偉基 2009 學位論文 ; thesis 49 en_US |
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碩士 === 國立清華大學 === 資訊工程學系 === 97 === Reducing power consumption is an significant issue in modern System-on-Chip designs. Multiple-supply voltages (MSV's) design is one of the effective ways for dynamic power reduction, and floorplanning is the appropriate stage in the physical design cycle for applying MSV's design. Previous works have addressed the MSV's design problem at floorplanning stage by solving the voltage assignment problem and the floorplanning problem separately. In this thesis, we propose a simulated annealing (SA) based voltage island-aware floorplanning algorithm to solve the two problems simultaneously. Our algorithm is based on corner block list [1] which is efficient for integrating the evaluation process of power costs function into SA. Experimental results show that our algorithm could save 31.63\% total power consumption by forming three voltage islands in average. We could obtain better deadspace, total wirelength and power consumption than the previous work [2] as well.
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author2 |
Mak, Wai-Kei |
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Mak, Wai-Kei Tang, Chih-Chieh 唐志傑 |
author |
Tang, Chih-Chieh 唐志傑 |
spellingShingle |
Tang, Chih-Chieh 唐志傑 Voltage Island-aware Floorplanning for SoC design |
author_sort |
Tang, Chih-Chieh |
title |
Voltage Island-aware Floorplanning for SoC design |
title_short |
Voltage Island-aware Floorplanning for SoC design |
title_full |
Voltage Island-aware Floorplanning for SoC design |
title_fullStr |
Voltage Island-aware Floorplanning for SoC design |
title_full_unstemmed |
Voltage Island-aware Floorplanning for SoC design |
title_sort |
voltage island-aware floorplanning for soc design |
publishDate |
2009 |
url |
http://ndltd.ncl.edu.tw/handle/32082571594069564724 |
work_keys_str_mv |
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