The PI/SI Effects on Ultra High-Speed and Low Voltage SDRAM I/O Circuits with Decoupling Capacitors
碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === This thesis presents a DDR4 I/O interface circuits operated at 1.1V and data rate is 3.2Gb/s. It is produced by standard UMC 90-nm CMOS process. In this chip, the transmitter and receiver circuits are included. To discuss the power integrity issue, we add many d...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/79290590134724170566 |