| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 97 === Many of the applications nowadays utilize the digital signal processing (DSP) to resolve the transmitted information. Therefore, an analog to digital interface is required between the received analog signal and DSP system and portable consumer electronics, the demand for low-power integrated circuits is indispensable. In many types of CMOS analog to digital converter (ADC) architectures, a pipelined architecture can archive good dynamic range performances and the same throughput as the flash ADC due to the pipelined operation in each range. This thesis focuses on the high-speed design of pipelined ADC. In the meanwhile, we try to minimize the power dissipations as well.
In this thesis, an 8-bit 50MHz pipelined A/D converter, with 1.5-bit resolution per stage, has been successfully designed and implemented using the TSMC 0.18μm 1P6M CMOS process. Simulation results show that the designed pipelined ADC can operate at 50MHz with 48.84dB signal- to- noise ratio – conforming to the 7.81-bit accuracy, and the estimated power dissipation is about 105 mw.
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