A Design Partitioning Approach for Three Dimensional Integrated Circuits
碩士 === 中原大學 === 電子工程研究所 === 98 === As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional integration circuits (3D ICs) technologies can help to improve circuit performance and reduce power consumption by shortening wirelength. In 3D IC, thro...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/vn227t |
| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 98 === As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional integration circuits (3D ICs) technologies can help to improve circuit performance and reduce power consumption by shortening wirelength. In 3D IC, through silicon vias (TSVs) are used to communicate signals between layers. However, TSV number problem and chip thermal problem are critical challenges for 3D IC circuit design. In this paper, we propose two approaches: (1) a heuristic algorithm to partition an integrated circuit with the objective to minimize the number of TSV and chip area; (2) An integer linear programming (ILP) approach to minimize the temperature. Experimental results consistently show that our approach works well in practice.
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