| Summary: | 博士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === This dissertation investigates comparator-based analog-to-digital converters (ADCs) in scaled CMOS technologies. Compared to amplifier-based ones, comparator-based ADCs have better potential in both speed and power efficiency. This dissertation presents not only theoretical analysis but also silicon verification. Three major chapters expound on the recent development of the flash ADC, binary-search ADC, and hybrid ADC designs. Each chapter first describes the motivation and background of each ADC. Then, the subsequent sections illustrate architecture modifications and circuit techniques. Finally, silicon prototypes are given as design examples to demonstrate the effectiveness and efficiency of the proposed techniques.
The flash-ADC part describes the basics of flash ADCs and discusses popular circuit techniques including resistive averaging network, interpolation and digital calibration. Both qualitative and quantitative analyses of these techniques are provided to give readers insights into flash ADC design. This part provides two 5-bit and above 3-GS/s prototypes: The first one is a conventional design with power consumption optimization and the other one uses a digital offset calibration method. In the following chapter, the dissertation presents a new ADC: binary-search ADC. This is an architecture between flash and SAR ADCs. The proposed ADC has a smaller comparator count than a conventional binary-search ADC. A binary-search ADC with a reduced comparator count shows good compromises between hardware, operation speed and power consumption. This chapter uses a 5-bit silicon prototype to demonstrate the high operation speed (800 MS/s) and power efficiency (around 100 fJ/conversion-step) of this ADC. This last part investigates the combinations of different ADC architectures. Since each ADC has its advantages and disadvantages compared to other ones, we can get benefits by combining different ADCs. This part shows the design and implementation of a combination of flash and SAR ADCs. The hybrid ADC consists of a flash coarse ADC and a SAR fine ADC, which exploits the high speed of a flash ADC and low power of a SAR ADC. Both theoretical and silicon results show this ADC improves sampling speed (150 to 200 MS/s) and linearity (＞ 70-dB SFDR) while still maintaining excellent power efficiency (around 20 fJ/conversion-step).
For system integration, the current design targets for the ADC are low power and small area. The proposed works in this dissertation cover a wide working range in both accuracy (5 to 9 bits) and speed (100 MS/s to 4 GS/s). Due to their excellent power efficiency and small active area, these ADCs are capable of being suitable building blocks in SoC applications.
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