Design and Implementation of Reconfigurable Inverse Transform Architecture for Multiple Purpose Video Coding

• Main Authors: Tsung-YuanHuang, 黃琮淵
• Other Authors: Gwo-Giun Lee
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/84341024631125085011

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === In this thesis, an area efficient reconfigurable inverse transformation architecture for multiple standards and a directed 2D reconfigurable Hadamard transform architecture for AVC/H.264 are proposed. We present top down design methodology with complexity analysis, commonalities extraction, and dataflow modeling to design reconfigurable architecture. By sharing the commonalities,the adder usage of the proposed reconfigurable inverse transform datapath can be reduced 44% compared with total amount of adders in performing transforms. Then, the reconfigurable architecture is synthesized using TSMC 0.18 technology cell library. The working frequency is 108Mhz, which is derived from the dataflow. The area synthesis result is 32k gates, which indicates that the proposed design has more efficient area than other documented design in VLSI implementation. In addition, the proposed architecture also satisfies the accuracy requirement of IEEE1180-1990 and ISO/IEC 23002-1 specification. Therefore, based on our top-down design approach and commonality extraction, the proposed designs have lower hardware cost and enough flexibility for multi-standard purposes with 1920×1088 resolution and 64 frames per second and the color format is 4:2:0 for real time processing.