Design and Implementation of UWB CMOS Low Noise Amplifiers and K Band Front-end Circuits for Radio Frequency Application

• Main Authors: Hao-Jhung Haung, 黃顥中
• Other Authors: Yo-Sheng Lin
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/11689919034215811835

碩士 === 國立暨南國際大學 === 電機工程學系 === 98 === This thesis aim is to design low noise amplifier and receiver front-end. Study the theme can be divided into four parts： In first part, 3.1 ~ 10.6 GHz low noise amplifier is designed for ultra wideband (UWB). This LNA composed of current-sharing technique to achieve low power. Because of the current-sharing technique have a disadvantage of insufficient bandwidth, we use inductive peaking technique to extend bandwidth. We use shunt-peaking technique to achieve output impedance matching. We present LNA in TSMC 0.18 m CMOS technology. This LNA achieved High 14.2dB gain, S11 and S22 are both below -10 dB, flat noise figure of 3.87~ 4.2 dB form 3.1 to 10.6 GHz. The result shows of power consuming 12 mW, and chip area is 0.747 mm2. In second part, 21~27 GHz low noise amplifier is suitable for radar system. To achieve sufficient gain, this LNA is composed of three cascaded common-source stages. The current-sharing technique with inductive peaking is adopted for bandwidth enhancement and in the second and third stage. In addition, we use microstrip line to replace inductors to achieve small chip size and helped to expect the measured result accurately. We present LNA in TSMC 0.18 m CMOS technology. This LNA achieved 11.83±0.97 dB gain, S11 below -8 dB, S22 below -13.3 dB, noise figure of 4.2~5.2 dB and smaller group-delay-variation ±13.8 ps form 21 to 27 GHz. The result shows of power consuming 27 mW, and chip area is 0.576 mm2. In third part, a K-band low noise amplifier with low power. This LNA is also composed of three cascaded common-source stages. The current-sharing technique is adopted for reduce current and achieve low power. Because of the quality factor of inductor is higher than microstrip line, we only replace part of inductors to achieve the best chip area. We present LNA in TSMC 0.18 m CMOS technology. This LNA achieved 8.85±0.75 dB gain, S11 below -8 dB, S22 below -10.8 dB, noise figure of 5.5~6.8 dB and small group-delay-variation ±17.8 ps over 21-27 GHz. The result shows of power consuming 5.4 mW, and chip area is 0.799 mm2. The results show that the LNA is suitable for low power radar systems. Finally, we have presented the K-band CMOS receiver front-end in TSMC 0.18um CMOS process. It consists of a low noise amplifier and a sub-harmonic mixer and converted RF signal to IF of 10MHz. The front-end makes the use of quadrature coupler and Marchand balun to achieve the needed phase difference. The measured results show the RF-to-IF isolation is below -33 dB, the LO-to-IF isolation is below -39 dB, the LO-to-RF, and 2LO-to-RF isolation is below -46 dB. The measured conversion gain at 24 GHz is 16 dB and the 1-dB gain compression point is -27 dBm. The measured RF port return loss over 21-27 GHz is below -10 dB and the LO port return loss at 12 GHz is below -10 dB. The measured phase difference of IFI and IFQ are 167.4° and 173.8°, respectively. The total power consumption is 47.7 mW, and chip area is 2.25 mm2.