| Summary: | 碩士 === 國立高雄大學 === 電機工程學系碩士班 === 98 === In the thesis, three types (finite impulse response, allpass, and infinite impulse response) of design on variable fractional-delay filters are proposed, and the technique of weighted-least-square method will be applied. For the implementation of the designed system, Farrow structure will be incorporated in the design of the stated variable fractional-delay filters. In the hardware design, shifting method takes the place of floating-point unit in order to decrease the complexity of circuits. The circuits are designed in Verilog harware description language with ModelSim. After making sure the fuctions are correct, we compare waveforms with the outcomes of theoretical computation. The schematics after synthesizing from Design Vision are showed in the end of each chapter. Area reports, timing reports, and power reports will be found in the appendix.
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