Design and Implementation of Variable Fractional-Delay Digital Filters
碩士 === 國立高雄大學 === 電機工程學系碩士班 === 98 === In the thesis, three types (finite impulse response, allpass, and infinite impulse response) of design on variable fractional-delay filters are proposed, and the technique of weighted-least-square method will be applied. For the implementation of the designed s...
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ndltd-TW-098NUK054420032016-05-04T04:31:50Z http://ndltd.ncl.edu.tw/handle/79482996781217230584 Design and Implementation of Variable Fractional-Delay Digital Filters 可調式分數延遲數位濾波器之設計與實現 Chen-Yang Wang 王振洋 碩士 國立高雄大學 電機工程學系碩士班 98 In the thesis, three types (finite impulse response, allpass, and infinite impulse response) of design on variable fractional-delay filters are proposed, and the technique of weighted-least-square method will be applied. For the implementation of the designed system, Farrow structure will be incorporated in the design of the stated variable fractional-delay filters. In the hardware design, shifting method takes the place of floating-point unit in order to decrease the complexity of circuits. The circuits are designed in Verilog harware description language with ModelSim. After making sure the fuctions are correct, we compare waveforms with the outcomes of theoretical computation. The schematics after synthesizing from Design Vision are showed in the end of each chapter. Area reports, timing reports, and power reports will be found in the appendix. Jong-Jy Shyu 徐忠枝 2010 學位論文 ; thesis 147 zh-TW |
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碩士 === 國立高雄大學 === 電機工程學系碩士班 === 98 === In the thesis, three types (finite impulse response, allpass, and infinite impulse response) of design on variable fractional-delay filters are proposed, and the technique of weighted-least-square method will be applied. For the implementation of the designed system, Farrow structure will be incorporated in the design of the stated variable fractional-delay filters. In the hardware design, shifting method takes the place of floating-point unit in order to decrease the complexity of circuits. The circuits are designed in Verilog harware description language with ModelSim. After making sure the fuctions are correct, we compare waveforms with the outcomes of theoretical computation. The schematics after synthesizing from Design Vision are showed in the end of each chapter. Area reports, timing reports, and power reports will be found in the appendix.
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Jong-Jy Shyu |
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Jong-Jy Shyu Chen-Yang Wang 王振洋 |
author |
Chen-Yang Wang 王振洋 |
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Chen-Yang Wang 王振洋 Design and Implementation of Variable Fractional-Delay Digital Filters |
author_sort |
Chen-Yang Wang |
title |
Design and Implementation of Variable Fractional-Delay Digital Filters |
title_short |
Design and Implementation of Variable Fractional-Delay Digital Filters |
title_full |
Design and Implementation of Variable Fractional-Delay Digital Filters |
title_fullStr |
Design and Implementation of Variable Fractional-Delay Digital Filters |
title_full_unstemmed |
Design and Implementation of Variable Fractional-Delay Digital Filters |
title_sort |
design and implementation of variable fractional-delay digital filters |
publishDate |
2010 |
url |
http://ndltd.ncl.edu.tw/handle/79482996781217230584 |
work_keys_str_mv |
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