The Study of Parameter Optimization of Wafer Level Chip Scale Packages in Board Level Drop Test with Taguchi's Method.

• Main Authors: Chun-Hung Tsai, 蔡俊弘
• Other Authors: Hsin-Hui Kuo
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/41574441483512758406

碩士 === 國立高雄大學 === 電機工程學系碩士班 === 98 === The study of the Wafer Level Chip Scale Packages（WLCSP）was carried out with reference to past experience in the laboratory and current industry standard as an effort to analyze various combinations of the multi-stages manufacturing processes of WLCSP. To find out the driving force that could improve the sustainability of the solder ball joints against the power of drop impact and the optimum process in making WLCSP, Taguchi's method was applied to plan out the experimentation. The materials tested and subjected to variations are the size and the thickness of Die, the composition of Solder ball, and the Ball’s diameter. According to Taguchi’s Method, the four variables aforementioned are the factors and each of them has three additional moving elements. The experimentation was designed to first discover the most influential factors, then adjust those factors, and thereby achieve the optimal combination. The ranking of influence of four factors determined in this study are Die size＞Die thickness＞Solder ball type＞Ball diameter. With further assistance from ANOVA analysis, the best design achieved is Die size of 4.0 4.0 mm2, Die thickness of 0.4 mm, Solder ball type of SAC105, and Ball diameter of 0.25 mm.