| Summary: | 碩士 === 國立臺北科技大學 === 自動化科技研究所 === 98 === Discrete Fourier Transform (DFT) is the mostly implemental method for phasor calculation. When frequency shifts, the leakage effect from DFT will occur during the phasor calculation. Because of the leakage effect, the calculated phasor values are not very accurate. In order to overcome this problem, basic Extended Discrete Fourier Transform (EDFT for short) can be used to diminishing the frequency shift phenomenon. Unfortunately, the harmonic components can also influence the results of computed phasor values.The basic EDFT cannot resolve this problem. The EDFT family that includes EDFT, harmonic EDFT and so on is extended from the basic DFT. By using the harmonic EDFT, the advantages of DFT can be maintained while, the above-mentioned problems can also be solved.
In this thesis, the harmonic EDFT is implemented using SOPC (System on a Programmable Chip) development system. The development system contains software and hardware. The VHDL module is verified by utilizing Modelsim simulator. The parallel computing property and looking-up method are implemented in the proposed system, the computation speed for DFT is improved quite substantially. The computed results from DFT are acquired by the NIOS II, a 32-bit RISC based microprocessor. When the phasor computation is completed, the signal information (i.e., amplitude, frequency, and phase angle) can be obtained. In order to verify and validate the performance of the developed system, controlled signals generated from a function generator is applied.
For the future extension, the hardware can be remained untouched while the software algorithm is modified for advanced applications.
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