Using Cell Characteristics to Minimize the Aging Effect on Clock Skew
碩士 === 中原大學 === 電子工程研究所 === 99 === In today’s VLSI design, clock gating is an effective approach to reduce dynamic power consumption. On the other hand, clock skew minimization is an important topic in clock tree synthesis. As the process technology advances, Negative Bias Temperature Instability (N...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/wxh5ww |