A High-Level Synthesis Approach for Minimum-Area Low-Power Gated Clock Designs
碩士 === 中原大學 === 電子工程研究所 === 99 === Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequential circuits. To effectively reduce the power consumption of clock tree, previous work has shown that clock control logic should be synthesized in the high-level...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/2xnt39 |