| Summary: | 博士 === 國立暨南國際大學 === 電機工程學系 === 99 === Abstract
This dissertation presents a study of high performance voltage controlled ring oscillators (VCRO) in standard CMOS process for multiple gigahertz applications. A differential delay cell with a novel complementary current control scheme is proposed for low-voltage and wide tuning-range VCROs. The proposed complementary current control scheme can extend the control voltage to cover the full-range of power supply voltage, which is unable to accomplish in a conventional VCRO. The full coverage of control voltage range not only widens the operation frequency range but also makes the circuit suitable for low-voltage operation. As the process technology is promoted to nanometer, the supply voltage drops below 1 V, the complementary current control scheme can continue to be applicable.
Using the proposed new differential delay cell, a voltage-controlled ring oscillator employing a three-stage structure and multiple-pass loop techniques, implemented in 0.18-μm 1P6M standard CMOS process, could achieve a wide tuning-range and very high-speed. Measured results for 1.8 V power supply show that a wide operation frequency range from 8.36-GHz to 1.29-GHz is accomplished for the full control voltage range of from 0 V to 1.8 V. The measured phase noise is -100.22 dBc/Hz at 1-MHz offset from the 8.35-GHz center frequency, and the figure of merit (FOM) is -159.95 dBc/Hz. When the supply voltage is reduced to 1 V, the operation frequency range is from 4.09-GHz to 0.479-GHz for the full control voltage range of from 0 V to 1 V. The measured phase noise is -94.22 dBc/Hz at 1-MHz offset from the 4.09-GHz center frequency, and the figure of merit (FOM) is -151.95 dBc/Hz. The chip core area without PAD is 106×76.2 μm2. By using these techniques, it may be possible to broaden the utilization of VCRO into some applications that previously required chip area consuming LC-tank oscillators.
Besides, for the application to microwave-band RFID system, we have designed a PLL employing the VCRO with the proposed new delay cell and the four-stage multiple-pass loop structure. The simulation of the PLL shows that when the supply voltage is 1 V and the operation frequency is 2.45-GHz, the lock time is 25 μs.
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